DS100BR111A Datasheet, PDF (24/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Address
0x00
Register
Name
Device ID
0x01
Control 1
0x02
Control 2
0x04
Control 3
0x05
0x06
CRC 1
CRC 2
TABLE 1. SMBus Register Map
Bits Field
Type Default EEPROM Description
Reg Bit
7 Reserved
R/W 0x00
set bit to 0
6:3 I2C Address [3:0]
R
[6:3] SMBus strap observation
2 EEPROM reading R
done
1: EEPROM Loading
0: EEPROM Done Loading
1 Reserved
RWS
C
Set bit to 0
0 Reserved
RWS
C
Set bit to 0
7:6 Idle Control
R/W 0x00
Yes Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
5:3 Reserved
R/W
Set bits to 0
2 LOS Select
R/W
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
1:0 Reserved
R/W
Set bits to 00'b
7 Reserved
R/W 0x00
Set bit to 0
6 Reserved
Set bit to 0
5 LOS override
Yes LOS pin override enable (1);
Use Normal Signal Detection (0)
4 LOS override value
Yes 1: Normal Operation
0: Output LOS
3 PWDN Inputs
2 PWDN Oscillator
Yes 1: PWDN
Yes ^{0: Normal Operation}
1 Reserved
0 Reserved
Yes Set bit to 0
7:6 eSATA Mode
Enable
R/W 0x00
Yes [7] Channel A (1)
[6] Channel B (1)
5 TX_DIS Override
Enable
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
4 TX_DIS Value
Channel A
1: TX Disabled
0: TX Enabled
3 TX_DIS Value
Channel B
2 Reserved
Set bit to 0'b
1:0 Reserved
Set bits to 00'b
7:0 CRC[7:0]
R/W 0x00
Slave Mode CRC Bits
7 Disable EEPROM R/W 0x10
CFG
Disable Master Mode EEPROM Configuration
6:5 Reserved
Set bits to 00'b
4 Reserved
Yes Set bit to 1'b
3 CRC Slave Mode
Enable
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED
register updates will NOT take effect until
correct CRC value is loaded
2:1 Reserved
Set bits to 00'b
0 CRC Enable
Slave CRC Trigger
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