DS100BR111A Datasheet, PDF (19/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Single EEPROM Header + Register Map with Default Value
EEPROM
Bit 7
Address Byte
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
0
Description
Value
Description 1
Value
2
Description
Value
CRC EN Address EEPROM > RES
COUNT[3]
Map
256 Bytes
Present
0
0
0
0
0
RES
RES
RES
RES
RES
0
0
0
0
0
Max
Max
Max
Max
Max
EEPROM EEPROM EEPROM EEPROM EEPROM
Burst size[7] Burst size[6] Burst size[5] Burst size[4] Burst size[3]
0
0
0
0
0
COUNT[2]
0
RES
0
Max
EEPROM
Burst size[2]
0
COUNT[1]
0
RES
0
Max
EEPROM
Burst size[1]
0
COUNT[0]
0
RES
0
Max
EEPROM
Burst size[0]
0
Description 3
Register
Value
Description 4
Register
Value
Description 5
Register
Value
Description 6
Register
Value
Description 7
Register
Value
Description 8
Register
Value
Description 9
Register
Value
Description 1
Register ⁰
Value
Description 1
Register ¹
Value
Description 1
Register ²
Value
Description 1
Register ³
Value
Description 1
Register ⁴
Value
Reserved
0x01 [7]
0
Ovrd_LOS
0x02 [5]
0
TX_DIS
CHA
0x04 [4]
0
Ovrd_IDLE
0x08 [4]
0
Reserved
0x0B [3]
0
CHA EQ[7]
0x0F [7]
0
A Sel scp
0x10 [7]
1
DEMA[2]
0x11 [2]
0
Idle auto B
0x15 [5]
0
CHB EQ[3]
0x16 [3]
1
Reserved
0x17 [3]
1
IDLE thA[1]
0x19 [3]
0
Reserved
0x01 [6]
0
LOS_Value
0x02 [4]
0
TX_DIS
CHB
0x04 [3]
0
Reserved
0x08 [3]
0
Reserved
0x0B [2]
0
CHA EQ[6]
0x0F [6]
0
Reserved
0x10 [6]
1
DEMA[1]
0x11 [1]
1
Idle sel B
0x15 [4]
0
CHB EQ[2]
0x16 [2]
1
Reserved
0x17 [2]
1
IDLE thA[0]
0x19 [2]
0
Reserved
0x01 [5]
0
PDWN Inp
0x02 [3]
0
Reserved
0x04 [2]
0
Reserved
0x08 [2]
0
Reserved
0x0B [1]
0
CHA EQ[5]
0x0F [5]
1
Reserved
0x10 [5]
1
DEMA[0]
0x11 [0]
0
Reserved
0x15 [3]
0
CHB EQ[1]
0x16 [1]
1
Reserved
0x17 [1]
0
IDLE thD[1]
0x19 [1]
0
Reserved Reserved Reserved Reserved Reserved
0x01 [4] 0x01 [3]
0x01 [2]
0x01 [1]
0x01 [0]
0
0
0
0
0
PWDN Osc Reserved
eSATA
Enable A
eSATA
Enable B
Ovrd
TX_DIS
0x02 [2] 0x02 [0]
0x04 [7]
0x04 [6]
0x04 [5]
0
0
0
0
0
Reserved Reserved
Reserved
Overide
IDLE_th
Reserved
0x04 [1] 0x04 [0]
0x06 [4]
0x08 [6]
0x08 [5]
0
0
1
0
0
Reserved Reserved Reserved Reserved Reserved
0x08 [1] 0x08 [0]
0x0B [6]
0x0B [5]
0x0B [4]
0
0
1
1
1
Reserved Idle auto A Idle sel A Reserved Reserved
0x0B [0] 0x0E [5]
0x0E [4]
0x0E [3]
0x0E [2]
0
0
0
0
0
CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0]
0x0F [4] 0x0F [3]
0x0F [2]
0x0F [1]
0x0F [0]
0
1
1
1
1
Reserved Reserved Reserved Reserved Reserved
0x10 [4] 0x10 [3]
0x10 [2]
0x10 [1]
0x10 [0]
0
1
1
0
1
CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0]
0x12 [7] 0x12 [3]
0x12 [2]
0x12 [1]
0x12 [0]
0
0
0
0
0
Reserved CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4]
0x15 [2] 0x16 [7]
0x16 [6]
0x16 [5]
0x16 [4]
0
0
0
1
0
CHB EQ[0] B Sel scp Reserved Reserved Reserved
0x16 [0] 0x17 [7]
0x17 [6]
0x17 [5]
0x17 [4]
1
1
1
1
0
Reserved CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow
0x17 [0] 0x18 [2]
0x18 [1]
0x18 [0]
0x19 [7]
1
0
1
0
0
IDLE thD[0] Reserved Reserved Reserved Reserved
0x19 [0]
0
0
0
0
0
19
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