DS100BR111A Datasheet, PDF (4/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Pin Descriptions
Pin Name
Pin Number
Differential High Speed I/O's
INA+, INA- ,
INB+, INB-,
24, 23
11, 12
OUTA+, OUTA-,
OUTB+, OUTB-,
Control Pins
ENSMB
7, 8
20, 19
3
ENSMB = 1 (SMBUS MODE)
SCL
5
SDA
4
AD0-AD3
10, 9, 2, 1
READEN#
17
DONE#
18
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
DEMA, DEMB
4, 5
TX_DIS
6
I/O, Type Pin Description
I, CML
O,CML
Inverting and non-inverting CML differential inputs to the
equalizer. An on-chip 50Ω termination resistor connects INx+ to
VDD and INx- to VDD when enabled.
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
I, LVCMOS
Float
System Management Bus (SMBus) enable pin
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
I, LVCMOS
O, Open
Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled. A clock input in Slave mode.
Can also be a clock output in Master mode.
I, LVCMOS,
O, Open
Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open
drain (pull-down only) output.
I, LVCMOS,
Float
(4-Levels)
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs. There are 16
addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device
SMBus address.
Note: Setting VOD_SEL = High in SMBus Mode will force the
Address = B0'h
I, LVCMOS When using an External EEPROM, a transition from high to low
starts the load from the external EEPROM
IO, LVCMOS, EEPROM Download Status
Float
HIGH indicates Error / Still Loading
(4-Levels) LOW indicates download complete. No Error.
I, LVCMOS,
Float
(4-Levels)
EQA/B, 0/1 control the level of equalization of each channel. The
EQA/B pins are active only when ENSMB is de-asserted (LOW).
When ENSMB goes high the SMBus registers provide
independent control of each lane, and the EQB0/B1 pins are
converted to SMBUS AD2/AD3 inputs. Table 3: Equalizer
Settings
IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins
Float
are only active when ENSMB is de-asserted (LOW). Each of the
(4-Levels) 4 A/B channels have the same level unless controlled by the
SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane and the DEM
pins are converted to SMBUS SCL and SDA pins.
Table 4: De-emphasis and Output Voltage Settings
I, LVCMOS
DS100BR111A
High = OUTA Enabled /OUTB Disabled
Low = OUTA/B Enabled
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