DS100BR111A Datasheet, PDF (17/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

In SMBus master mode the DS100BR111A reads its initial configuration from an external EEPROM upon power-up. Some of the
pins of the DS100BR111A perform the same functions in SMBus master and SMBus slave mode. Once the DS100BR111A has
finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and
can be further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and
can be omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus
master mode.
• DONE#
• READEN#
When the DS100BR111A is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the
READEN# pin goes low. When the DS100BR111A is finished reading its configuration from the external EEPROM, it drives the
DONE# pin low. In applications where there is more than one DS100BR111A on the same SMBus, bus contention can result if
more than one DS100BR111A tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this
bus contention. The system should be designed so that the READEN# pin from one DS100BR111A in the system is driven low on
power-up. This DS100BR111A will take command of the SMBus on power-up and will read its initial configuration from the external
EEPROM. When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the
READEN# pin of another DS100BR111A. When this DS100BR111A senses its READEN# pin driven low, it will take command of
the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting
the DONE# pin of each DS100BR111A to the READEN# pin of the next DS100BR111A, each DS100BR111A can read its initial
configuration from the EEPROM without causing bus contention.
FIGURE 7. Typical multi-device EEPROM connection diagram
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