DS100BR111A Datasheet, PDF(14/35 Page) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A Datasheet, PDF (14/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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APPLICATIONS INFORMATION

4-Level Input Configuration Guidelines

The 4-level input pins utilize a resistor divider to help set the

4 valid levels. There is an internal 30K pull-up and a 60K pull-

down connected to the package pin. These resistors, together

with the external resistor connection combine to achieve the

desired voltage level. Using the 1K pull-up, 1K pull-down, no

connect, and 20K pull-down provide the optimal voltage levels

for each of the four input states.

Table 6: 4-Level Input Voltage

Level

Setting

3.3V Mode

2.5V Mode

0 01K to GND

0.1 V

0.08 V

R 20K to GND

0.33 * VIN

FLOAT

0.67 * VIN

1K to VDD/VIN

VIN - 0.05V

0.33 * VDD

0.67 * VDD

VIN - 0.04V

â¢ Typical 4-Level Input Thresholds

â Level 1 - 2 = 0.2 VIN or VDD

â Level 2 - 3 = 0.5 VIN or VDD

â Level 3 - 4 = 0.8 VIN or VDD

In order to minimize the startup current associated with the

integrated 2.5V regulator the 1K pull-up / pull-down resistors

are recommended. If several 4 level inputs require the same

setting, it is possible to combine two or more 1K resistors into

a single lower value resistor. As an example; combining two

inputs with a single 500â¦ resistor is a good way to save board

space.

PCB Layout Guidelines

The CML inputs and outputs have been optimized to work with

interconnects using a controlled differential impedance of 85

- 100â¦. It is preferable to route differential lines exclusively on

one layer of the board, particularly for the input traces. The

use of vias should be avoided if possible. If vias must be used,

they should be used sparingly and must be placed symmet-

rically for each side of a given differential pair. Whenever

differential vias are used the layout must also provide for a

low inductance path for the return currents as well. Route the

differential signals away from other signals and noise sources

on the printed circuit board. See AN-1187 for additional infor-

mation on LLP packages.

Different transmission line topologies can be used in various

combinations to achieve the optimal system performance.

Impedance discontinuities at vias can be minimized or elimi-

nated by increasing the swell around each hole and providing

for a low inductance return current path. When the via struc-

ture is associated with thick backplane PCB, further optimiza-

tion such as back drilling is often used to reduce the

detrimental high frequency effects of stubs on the signal path.

Power Supply Configuration Guidelines

The DS100BR111A can be configured for 2.5V operation or

3.3V operation. The lists below outline required connections

for each supply selection.

3.3V Mode of Operation

1. Tie VDD_SEL = 0 with 1K resistor to GND.

2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling

at VIN is recommended.

3. See information on VDD bypass below.

4. SDA and SCL pins should connect pull-up resistor to VIN

5. Any 4-Level input which requires a connection to "Logic

1" should use a 1K resistor to VIN

2.5V Mode of Operation

1. VDD_SEL = Float

2. VIN = Float

3. Feed 2.5V supply into VDD pins.

4. See information on VDD bypass below.

5. SDA and SCL pins connect pull-up resistor to VDD for

2.5V uC SMBus IO

6. SDA and SCL pins connect pull-up resistor to VDD for

3.3V uC SMBus IO

7. Any 4-Level input which requires a connection to "Logic

1" should use a 1K resistor to VIN

Note: The DAP (bottom solder pad) is the GND connection.

Power Supply Bypass

Two approaches are recommended to ensure that the

DS100BR111A is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be

connected to power planes routed on adjacent layers of the

printed circuit board. The layer thickness of the dielectric

should be minimized so that the VDD and GND planes create

a low inductance supply with distributed capacitance. Sec-

ond, careful attention to supply bypassing through the proper

use of bypass capacitors is required. A 0.1 Î¼F bypass capac-

itor should be connected to each VDD pin such that the ca-

pacitor is placed as close as possible to the device. Smaller

body size capacitors can help facilitate proper component

placement.

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