TMS320DM643AZDK5 Datasheet, PDF (77/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
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SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
5.6 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The
RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core
and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held
low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should
be at their proper operating conditions and CLKIN should also be running at the correct frequency.
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section
of this data manual.
5.6.1 Reset Electrical Data/Timing
Table 5-10. Timing Requirements for Reset (see Figure 5-11)
NO.
1
t_w(RST)
16 t_su(boot)
17 t_h(boot)
Width of the RESET pulse
Setup time, boot configuration bits valid before RESET high ⁽¹⁾
Hold time, boot configuration bits valid after RESET high ⁽¹⁾
(1) AEA[22:19], LENDIAN, and HD5 are the boot configuration pins during device reset.
(2) E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
(3) P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
–500
–600
MIN
250
4E or 4C⁽²⁾
4P ⁽³⁾
MAX
UNIT
µs
ns
ns
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DM643 Peripheral Information and Electrical Specifications
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