TMS320DM643AZDK5 Datasheet, PDF (134/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
5.13.3.2 Video Data and Control Timing (Video Capture Mode)
www.ti.com
Table 5-53. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 5-54)
NO.
1 t_{su(VDATV-VKIH)} Setup time, VPxDx valid before VPxCLKINx high
2 t_{h(VDATV-VKIH)} Hold time, VPxDx valid after VPxCLKINx high
3 t_{su(VCTLV-VKIH)} Setup time, VPxCTLx valid before VPxCLKINx high
4 t_{h(VCTLV-VKIH)} Hold time, VPxCTLx valid after VPxCLKINx high
–500
–600
MIN MAX
2.9
0.5
2.9
0.5
UNIT
ns
ns
ns
ns
VPxCLKINx
1
2
VPxD[19:0] (Input)
3
4
VPxCTLx (Input)
Figure 5-54. Video Port Capture Data and Control Input Timing
134 DM643 Peripheral Information and Electrical Specifications
Copyright © 2005–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM643