TMS320DM643AZDK5 Datasheet, PDF (122/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
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5.12 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
On the DM643 device, the McBSP peripheral does not support external clocking to the sample rate
generator (no CLKS input).
For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel
Buffered Serial Port (McBSP) Reference Guide (literature number SPRU580).
5.12.1 McBSP Peripheral Register Description(s)
HEX ADDRESS RANGE
ACRONYM
Table 5-40. McBSP 0 Registers
REGISTER NAME
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 – 0x33FF FFFF
018C 0004
0x3000 0000 – 0x33FF FFFF
018C 0008
018C 000C
018C 0010
018C 0014
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 – 018F FFFF
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCERE00
XCERE00
PCR0
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
McBSP0 receive control register
McBSP0 transmit control register
McBSP0 sample rate generator register
McBSP0 multichannel control register
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
CLKSP (Bit 30) and CLKSM
(Bit 29) are RSV on DM643
122 DM643 Peripheral Information and Electrical Specifications
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