TMS320DM643AZDK5 Datasheet, PDF (1/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
www.ti.com
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
Check for Samples: TMS320DM643
1 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor
1234
• High-Performance Digital Media Processor
– 2-, 1.67-ns Instruction Cycle Time
– 500-, 600-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 4000, 4800 MIPS
– Fully Software-Compatible With C64x™
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2™ Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Synchronous Memories (SDRAM, SBSRAM,
ZBT SRAM, and FIFO)
– 1024M-Byte Total Addressable External
Memory Space
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 10/100 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Media Independent Interface (MII)
– 8 Independent Transmit (TX) Channels and 1
Receive (RX) Channel
• Management Data Input/Output (MDIO)
• Two Configurable Video Ports (VP1, VP2)
Arithmetic per Clock Cycle
– Providing a Glueless I/F to Common Video
• Two Multipliers Support Four 16 x 16-Bit
Decoder and Encoder Devices
Multiplies (32-Bit Results) per Clock
– Supports Multiple Resolutions/Video Stds
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
• Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• Host-Port Interface (HPI) [32-/16-Bit]
• Multichannel Audio Serial Port (McASP)
– Eight Serial Data Pins
– Wide Variety of I²S and Similar Bit Stream
Format
– Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3, CP-430
– 8-Bit Overflow Protection
Formats
– Bit-Field Extract, Set, Clear
• Inter-Integrated Circuit ( I²C Bus™)
– Normalization, Saturation, Bit-Counting
• Multichannel Buffered Serial Port
– VelociTI.2™ Increased Orthogonality
– CLKS Input Not Supported
• L1/L2 Memory Architecture
• Three 32-Bit General-Purpose Timers
– 128K-Bit (16K-Byte) L1P Program Cache
• Sixteen General-Purpose I/O (GPIO) Pins
(Direct Mapped)
• Flexible PLL Clock Generator
– 128K-Bit (16K-Byte) L1D Data Cache (2-Way
Set-Associative)
• IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
– 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
• Endianess: Little Endian, Big Endian
• 548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
• 548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
• 64-Bit External Memory Interface (EMIF)
• 0.13-µm/6-Level Cu Metal Process (CMOS)
– Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
• 3.3-V I/O, 1.2-V Internal (-500)
• 3.3-V I/O, 1.4-V Internal (-600)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Windows is a registered trademark of Microsoft Corporation.
2
I²C Bus is a trademark of Philips Electronics N.V.
3
All other trademarks are the property of their respective owners.
4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2010, Texas Instruments Incorporated