TMS320DM643AZDK5 Datasheet, PDF (26/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
STCLK^(C)
VP2CLK0
VP2CLK1
VP2CTL0
VP2CTL1
VP2CTL2
Timing and
Control Logic
VP2D[0]
VP2D[1]
VP2D[2]
VP2D[3]
VP2D[4]
VP2D[5]
VP2D[6]
VP2D[7]
VP2D[8]
VP2D[9]
Capture/Display
Buffer
(2560 Bytes)
Channel A^(A)
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VP2D[10]
VP2D[11]
VP2D[12]
VP2D[13]
VP2D[14]
VP2D[15]
VP2D[16]
VP2D[17]
VP2D[18]
VP2D[19]
Capture/Display
Buffer
(2560 Bytes)
Channel B uses only
the VP2D[19:10]
bidirectional pins
Channel B^(B)
Video Port 2 (VP2)
A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656 (8/10-bit), Y/C
Video (16/20-bit), RAW Video (16/20-bit) capture modes [TSI (8-bit) capture mode].
B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW Video data with
Channel A.
C. The same STCLK signal is used for both video ports (VP1 and VP2).
Figure 2-13. Video Port 2 Peripheral Signals
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