TMS320DM643AZDK5 Datasheet, PDF (136/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
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Table 5-56. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx^{(1) (2)}
(see Figure 5-56)
NO.
PARAMETER
–500
–600
MIN
MAX
1 t_c(VKO)
2 t_w(VKOH)
3 t_w(VKOL)
4 t_t(VKO)
5 t_d(VKIH-VKOH)
6 t_d(VKIL-VKOL)
7 t_d(VKIH-VKOL)
8 t_d(VKIL-VKOH)
9 t_{d(VKIH-VPOUTV)}
10 t_{d(VKIH-VPOUTIV)}
11 t_{d(VKOH-VPOUTV)}
12 t_{d(VKOH-VPOUTIV)}
Cycle time, VPxCLKOUTx
Pulse duration, VPxCLKOUTx high
Pulse duration, VPxCLKOUTx low
Transition time, VPxCLKOUTx
Delay time, VPxCLKINx high to VPxCLKOUTx high⁽³⁾
Delay time, VPxCLKINx low to VPxCLKOUTx low⁽³⁾
Delay time, VPxCLKINx high to VPxCLKOUTx low
Delay time, VPxCLKINx low to VPxCLKOUTx high
Delay time, VPxCLKINx high to VPxOUT valid⁽⁴⁾
Delay time, VPxCLKINx high to VPxOUT invalid⁽⁴⁾
Delay time, VPxCLKOUTx high to VPxOUT valid^{(1) (4)}
Delay time, VPxCLKOUTx high to VPxOUT invalid^{(1) (4)}
V – 0.7
VH – 0.7
VL – 0.7
1.1
1.1
1.1
1.1
1.7
–0.2
V + 0.7
VH + 0.7
VL + 0.7
1.8
5.7
5.7
5.7
5.7
9
4.3
(1) V = the video input clock (VPxCLKINx) period in ns.
(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
(3) Assuming non-inverted VPxCLKOUTx signal.
(4) VPxOUT consists of VPxCTLx and VPxD[19:0]
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
5
2
1
3
6
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
4
7
11
4
8
12
VPxCTLx,V
PxD[19:0]
(Outputs)
9
15
10
16
VPxCTLx
(Input)
14
13
Figure 5-56. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx
136 DM643 Peripheral Information and Electrical Specifications
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