TMS320DM643AZDK5 Datasheet, PDF (108/164 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM643
SPRS269D – FEBRUARY 2005 – REVISED OCTOBER 2010
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 0)^†
ACLKR/X (CLKRP = CLKXP = 1)^‡
AFSR/X (Bit Width, 0 Bit Delay)
4
3
4
6
5
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
8
7
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
† _{For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling}
edge (to shift data in).
‡ _{For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising}
edge (to shift data in).
Figure 5-35. McASP Input Timings
108 DM643 Peripheral Information and Electrical Specifications
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