MSP430F677X_16 Datasheet, PDF (77/162 Pages) Texas Instruments – Polyphase Metering SoCs

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ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x, MSP430F676x, MSP430F674x
SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013
UCMODEx = 01
STE
UCMODEx = 10
UCLK
CKPL = 0
CKPL = 1
SOMI
t_STE,LEAD
1/f_UCxCLK
t_LOW/HIGH
t_LOW/HIGH
t_STE,LAG
t_SU,MI
t_HD,MI
SIMO
t_STE,ACC
t_VALID,MO
Figure 14. SPI Master Mode, CKPH = 1
t_STE,DIS
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE low to clock
TEST CONDITIONS
V_CC
MIN TYP
2V
4
3V
3
t_STE,LAG STE lag time, Last clock to STE high
2V
0
3V
0
2V
t_STE,ACC STE access time, STE low to SOMI data out
3V
t_STE,DIS
STE disable time, STE high to SOMI high
impedance
2V
3V
t_SU,SI
SIMO input data setup time
2V
2
3V
1
t_HD,SI
SIMO input data hold time
2V
2
3V
2
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
2V
C_L = 20 pF
3V
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
2V
24
3V
16
MAX UNIT
ns
ns
46
ns
24
38
ns
25
ns
ns
55
ns
32
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
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