MSP430F677X_16 Datasheet, PDF (19/162 Pages) Texas Instruments – Polyphase Metering SoCs

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x, MSP430F676x, MSP430F674x
www.ti.com
TERMINAL
NAME
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/LCDREF/
R13
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
P2.7/PM_UCB0CLK/CB2
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
P4.0/PM_UCA2CLK/S32
SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013
Table 5. Terminal Functions – PZ Package (continued)
NO. I/O⁽¹⁾
PZ
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out, master in
48 I/O _{Default mapping: eUSCI_B0 I2C clock}
External reference voltage input for regulated LCD voltage
Input/Output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function
49 I/O ^{Default mapping: eUSCI_B0 SPI slave in, master out}
Default mapping: eUSCI_B0 I2C data
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
50 I/O _{Default mapping: eUSCI_B0 clock input/output}
Comparator_B input CB2
General-purpose digital I/O with mappable secondary function
51 I/O _{Default mapping: eUSCI_A0 UART receive data}
Default mapping: eUSCI_A0 SPI slave out, master in
General-purpose digital I/O with mappable secondary function
52 I/O ^{Default mapping: eUSCI_A0 UART transmit data}
Default mapping: eUSCI_A0 SPI slave in, master out
LCD segment output S39
General-purpose digital I/O with mappable secondary function
53 I/O _{Default mapping: eUSCI_A0 clock input/output}
LCD segment output S38
General-purpose digital I/O with mappable secondary function
54 I/O _{Default mapping: eUSCI_A1 clock input/output}
LCD segment output S37
General-purpose digital I/O with mappable secondary function
55 I/O ^{Default mapping: eUSCI_A1 UART receive data}
Default mapping: eUSCI_A1 SPI slave out, master in
LCD segment output S36
General-purpose digital I/O with mappable secondary function
56 I/O ^{Default mapping: eUSCI_A1 UART transmit data}
Default mapping: eUSCI_A1 SPI slave in, master out
LCD segment output S35
General-purpose digital I/O with mappable secondary function
57 I/O ^{Default mapping: eUSCI_A2 UART receive data}
Default mapping: eUSCI_A2 SPI slave out, master in
LCD segment output S34
General-purpose digital I/O with mappable secondary function
58 I/O ^{Default mapping: eUSCI_A2 UART transmit data}
Default mapping: eUSCI_A2 SPI slave in, master out
LCD segment output S33
General-purpose digital I/O with mappable secondary function
59 I/O _{Default mapping: eUSCI_A2 clock input/output}
LCD segment output S32
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19