MSP430F677X_16 Datasheet, PDF (15/162 Pages) Texas Instruments – Polyphase Metering SoCs

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x, MSP430F676x, MSP430F674x
www.ti.com
SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013
TERMINAL
NAME
P2.1/PM_TA0.1/BSL_RX
P2.2/PM_TA0.2
P2.3/PM_TA1.0
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
RST/NMI/SBWTDIO
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
SD3P0
SD3N0
VASYS2
AVSS2
VREF
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
Table 4. Terminal Functions – PEU Package (continued)
NO. I/O⁽¹⁾
PEU
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable secondary function
94 I/O _{Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output}
Bootstrap loader: Data receive
95 I/O ^{General-purpose digital I/O with port interrupt and mappable secondary function}
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
96 I/O ^{General-purpose digital I/O port interrupt and with mappable secondary function}
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
97
I ^{Test mode pin – select digital I/O on JTAG pins}
Spy-Bi-Wire input clock
98 I/O ^{General-purpose digital I/O}
Test data output
99 I/O ^{General-purpose digital I/O}
Test data input or Test clock input
100 I/O ^{General-purpose digital I/O}
Test mode select
101 I/O ^{General-purpose digital I/O}
Test clock
Reset input active low⁽³⁾
102 I/O _{Non-maskable interrupt input}
Spy-By-Wire data input/output
103 I _{SD24_B positive analog input for converter 0}⁽⁴⁾
104 I _{SD24_B negative analog input for converter 0}⁽⁴⁾
105 I _{SD24_B positive analog input for converter 1}⁽⁴⁾
106 I _{SD24_B negative analog input for converter 1}⁽⁴⁾
107 I _{SD24_B positive analog input for converter 2}⁽⁴⁾
108 I _{SD24_B negative analog input for converter 2}⁽⁴⁾
109 I _{SD24_B positive analog input for converter 3}⁽⁴⁾
110 I _{SD24_B negative analog input for converter 3}⁽³⁾
111
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of C_VSYS
112
Analog ground supply
113 I _{SD24_B external reference voltage}
114 I _{SD24_B positive analog input for converter 4}⁽⁴⁾ _{(not available on F674x devices)}
115 I _{SD24_B negative analog input for converter 4}⁽⁴⁾ _{(not available on F674x devices)}
116 I _{SD24_B positive analog input for converter 5}⁽⁴⁾ _{(not available on F674x devices)}
117 I _{SD24_B negative analog input for converter 5}⁽⁴⁾ _{(not available on F674x devices)}
118 I _{SD24_B positive analog input for converter 6}⁽⁴⁾ _{(not available on F676x, F674x devices)}
119 I _{SD24_B negative analog input for converter 6}⁽⁴⁾ _{(not available on F676x, F674x devices)}
120
Analog ground supply
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(4) It is recommended to short unused analog input pairs and connect them to analog ground.
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