MSP430F677X_16 Datasheet, PDF (4/162 Pages) Texas Instruments – Polyphase Metering SoCs

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x, MSP430F676x, MSP430F674x
SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
Family members available are summarized in Table 1.
Table 1. Family Members⁽¹⁾⁽²⁾
Device
MSP430F6779IPEU
MSP430F6778IPEU
MSP430F6777IPEU
MSP430F6776IPEU
MSP430F6775IPEU
MSP430F6769IPEU
MSP430F6768IPEU
MSP430F6767IPEU
MSP430F6766IPEU
MSP430F6765IPEU
MSP430F6749IPEU
MSP430F6748IPEU
MSP430F6747IPEU
MSP430F6746IPEU
MSP430F6745IPEU
MSP430F6779IPZ
MSP430F6778IPZ
MSP430F6777IPZ
MSP430F6776IPZ
MSP430F6775IPZ
MSP430F6769IPZ
MSP430F6768IPZ
MSP430F6767IPZ
MSP430F6766IPZ
MSP430F6765IPZ
MSP430F6749IPZ
MSP430F6748IPZ
MSP430F6747IPZ
MSP430F6746IPZ
MSP430F6745IPZ
Flash
(KB)
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
512
512
256
256
128
SRAM
(KB)
SD24_B
Converters
ADC10_A
Channels
32
7
6 ext, 2 int
16
7
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
16
7
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
16
6
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
16
4
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
32
7
6 ext, 2 int
16
7
6 ext, 2 int
16
7
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
32
6
6 ext, 2 int
16
6
6 ext, 2 int
16
6
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
32
4
6 ext, 2 int
16
4
6 ext, 2 int
16
4
6 ext, 2 int
Timer_A ⁽³⁾
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
eUSCI
Channel A: Channel B:
I/O
UART, IrDA, SPI, I²C
SPI
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
90
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
4
2
62
Package
Type
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
128 PEU
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
4
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