OMAPL138B-EP Datasheet, PDF (72/282 Pages) Texas Instruments – OMAPL138B C6-Integra DSP+ARM Processor

OMAPL138B-EP
SPRS815B – DECEMBER 2011 – REVISED MARCH 2012
Table 2-34. Unused RTC Signal Configuration (continued)
SIGNAL NAME
RTC_CVDD
RTC_VSS
Configuration
Connect to CVDD
VSS
www.ti.com
Table 2-35. Unused DDR2/mDDR Controller Signal Configuration
SIGNAL NAME
DDR_D[15:0]
DDR_A[13:0]
DDR_CLKP
DDR_CLKN
DDR_CKE
DDR_WE
DDR_RAS
DDR_CAS
DDS_CS
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_BA[2:0]
DDR_DQGATE0
DDR_DQGATE1
DDR_ZP
DDR_VREF
DDR_DVDD18
Configuration ⁽¹⁾
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
(1) To minimize power consumption, the DDR2/mDDR controller input receivers should be placed in power-down mode by setting
VTPIO[14]=1.
72
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