OMAPL138B-EP Datasheet, PDF (122/282 Pages) Texas Instruments – OMAPL138B C6-Integra DSP+ARM Processor

OMAPL138B-EP
SPRS815B – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
Table 5-23. Timing Requirements for EMIFA Asynchronous Memory Interface ⁽¹⁾
NO.
PARAMETER
E t_c(CLK)
2 t_{w(EM_WAIT)}
12 t_{su(EMDV-EMOEH)}
13 t_{h(EMOEH-EMDIV)}
14 t_{su (EMOEL-EMWAIT)}
28 t_{su (EMWEL-EMWAIT)}
READS and WRITES
Cycle time, EMIFA module clock
Pulse duration, EM_WAIT assertion and deassertion
READS
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
Setup Time, EM_WAIT asserted before end of Strobe
Phase ⁽²⁾
WRITES
Setup Time, EM_WAIT asserted before end of Strobe
Phase ⁽²⁾
1.3V, 1.2V
1.1V
1.0V
UNIT
MIN MAX MIN MAX MIN MAX
6.75
15
20
ns
2E
2E
2E
ns
3
5
7
ns
0
0
0
ns
4E+3
4E+3
4E+3
ns
4E+3
4E+3
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 5-17 and Figure 5-18 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
122 Peripheral Information and Electrical Specifications
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