OMAPL138B-EP Datasheet, PDF (1/282 Pages) Texas Instruments – OMAPL138B C6-Integra DSP+ARM Processor

OMAPL138B-EP
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SPRS815B – DECEMBER 2011 – REVISED MARCH 2012
OMAPL138B C6-Integra™ DSP+ARM® Processor
Check for Samples: OMAPL138B-EP
1 OMAPL138B C6-Integra™ DSP+ARM® Processor
1.1 Features
1
• Highlights
• C674x Two Level Cache Memory Architecture
– Dual Core SoC
– 32K-Byte L1P Program RAM/Cache
• 345-MHz ARM926EJ-S™ RISC MPU
– 32K-Byte L1D Data RAM/Cache
• 345-MHz C674x Fixed/Floating-Point VLIW
– 256K-Byte L2 Unified Mapped RAM/Cache
DSP
– Flexible RAM/Cache Partition (L1 and L2)
– Supports TI’s Basic Secure Boot
• Enhanced Direct-Memory-Access Controller 3
– Enhanced Direct-Memory-Access Controller
(EDMA3):
(EDMA3)
– 2 Channel Controllers
– Serial ATA (SATA) Controller
– 3 Transfer Controllers
– DDR2/Mobile DDR Memory Controller
– 64 Independent DMA Channels
– Two Multimedia Card (MMC)/Secure Digital
(SD) Card Interface
– LCD Controller
– Video Port Interface (VPIF)
– 10/100 Mb/s Ethernet MAC (EMAC)
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
– Load-Store Architecture With Non-Aligned
Support
– Programmable Real-Time Unit Subsystem
– 64 General-Purpose Registers (32 Bit)
– Three Configurable UART Modules
– Six ALU (32-/40-Bit) Functional Units
– USB 1.1 OHCI (Host) With Integrated PHY
• Supports 32-Bit Integer, SP (IEEE Single
– One Multichannel Audio Serial Port
Precision/32-Bit) and DP (IEEE Double
– Two Multichannel Buffered Serial Ports
Precision/64-Bit) Floating Point
• Dual Core SoC
– 345-MHz ARM926EJ-S™ RISC MPU
– 345-MHz C674x Fixed/Floating-Point VLIW
DSP
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP → SP Per Clock
– 2 SP x SP → DP Every Two Clocks
– 2 SP x DP → DP Every Three Clocks
– 2 DP x DP → DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
• C674x™ Instruction Set Features
Multiplies, or Eight 8 x 8-Bit Multiplies per
– Superset of the C67x+™ and C64x+™ ISAs
Clock Cycle, and Complex Multiples
– Up to 3648/2746 C674x MIPS/MFLOPS
– Instruction Packing Reduces Code Size
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– All Instructions Conditional
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
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– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
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