TL16PNP200 Datasheet, PDF (7/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
default format
On power up or reset, the TL16PNP200 starts generating read operations to the EEPROM. Each read
transaction consists of read opcode, address, and data cycles (see EEPROM section). The data cycle is
comprised to 16-bits. EEPROM addresses 0x00 through 0x0D store the power-up defaults. These defaults
include the PnP configuration register defaults, I/O block size, DMA mapping, and OEN configuration. Table 1
is a description of the format for storing the defaults in the EEPROM.
Table 1. Default Format
ADDRESS
DESCRIPTION
0x00
LD0 Memory base address bits 23-8 (Note 1)
0x01
LD1 Memory base address bits 23-8 (Note 1)
0x02
LD0 Memory upper address bits 23-8 (Note 1)
0x03
LD1 Memory upper address bits 23-8 (Note 1)
0x04
LD0 I/O Base address bits 15-0
0x05
LD1 I/O Base address bits 15-0
0x06
LD2 I/O Base address bits 15-0 (Note 2)
0x07
LD3 I/O Base address bits 15-0 (Note 2)
0x08
LD4 I/O Base address bits 15-0 (Note 2)
0x09
Bits 15-13: LD0 I/O block size, bits 12-10: LD1 I/O block size, bits 9-7: LD2 I/O block size, bits 6-4: LD3 I/O block size, bits
3-1: LD4 I/O block size (Note 3)
0x0A
Bits 15-12: LD0 IRQ level, bits 11-8: LD1 IRQ level, bits 7-4: LD2 IRQ level, bits 3-0: LD3 IRQ level (Note 4)
0x0B
Bits 15-12: LD4 IRQ level, bits 11-9 LD0: DMA channel, bits 8-6: LD1 DMA channel (Note 5)
0x0C
Bit 15: LD0 active, bit 14: LD1 active, bit 13: LD2 active, bit 12: LD3 active, bit 11: LD4 active, bits 10-8: OEN0 configuration,
bits 7-5: OEN1 configuration, bit 4: mode (Note 6)
0x0D
Bits 14-12: DMA 4 mapping, bits 11-9: DMA 3 mapping, bits 8-6: DMA 2 mapping, bits 5-3: DMA 1 mapping,
bits 2-0: DMA 0 mapping (Note 7)
NOTES:
1. In Mode 1, these fields are ignored.
2. In Mode 0, these fields are ignored.
3. Bit 0 is unused, and in Mode 0 bits 9-1 are ignored.
4. In Mode 0 bits 7-0 are ignored.
5. Bits 5-0 are unused, and in Mode 0 bits 15-12 are ignored.
6. Bits 3-0 are unused, and in Mode 0 bits 13-11 and bits 7-5 are ignored.
7. Bit 15 is unused, and in Mode 0 bits 14-9 are ignored.
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