TL16PNP200 Datasheet, PDF (10/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP† MAX UNIT
VOH
VOL
Il
IOZ
High-level output voltage
Low-level output voltage
Input current
High-impedance-state output
current
IOH = − 4 mA (see Note 10)
IOH = − 12 mA (see Note 11)
IOL = 4 mA (see Note 10)
IOL = 12 mA (see Note 11)
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other pins floating
VCC = 5.25 V,
VSS = 0,
VO = 0 to 5.25 V,
Pullup transistors and pulldown transistors are off
VCC −0.8
VCC −0.8
V
0.5
V
0.5
± 1 µA
± 10 µA
ICC
Supply current
VCC = 5.25 V,
All inputs toggle
No load on outputs
TA = 25°C,
f = 22 MHz,
25
mA
Ci(CLK) Clock input capacitance
fCLK
Clock frequency
† _{All typical values are at VCC = 5 V and TA = 25°C.}
NOTES: 10. These parameters apply for all outputs except D7 −D0, IRQ and CDRQ outputs.
11. These parameters only apply for D7 −D0, IRQ , and CDRQ outputs.
5
pF
10
22 MHz
serial EEPROM clock timing requirements over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN MAX UNIT
tw(SCLKH)
tw(SCLKL)
fCLK
Pulse duration, SCLK high to low (see Note 12)
Pulse duration, SCLK low to high (see Note 12)
SCLK clock frequency (see Note 13)
tCHCL
tCLCH
See Figure 9
250
ns
250
ns
0.3 0.68 MHz
td1
Delay time, CS high to SCLK high
td2
Delay time, SIO input valid to SCLK high
tpd1
Propagation delay time, SCLK high to input level
transition
tSHCH
See Figure 9
50
ns
tDVCH
100
ns
See Figures 9 and 10
tCHDX
100
ns
tpd2
Propagation delay time, SCLK high to output valid
tpd3
Propagation delay time, SCLK low to CS transition
tCHQV
tCLSL
See Figure 10
500 ns
2
clock
period
td3
Delay time, CS low to output Hi-Z
tSLQZ
100 ns
NOTES: 12. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles per the
ST93C56 specification.
13. The SCLK signal is attained by dividing the internal CLK signal frequency by 32.
10
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