TL16PNP200 Datasheet, PDF (21/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
PRINCIPLES OF OPERATION
READ op code transfer (see Figure 9)
Initially, the chip select signal,S, of the EEPROM, which connects to the TL16PNP200 EEPROM chip select
(SCS), is raised. The data D and Q of the EEPROM then sample the TL16PNP200 (SIO) line on the following
rising edges of the TL16PNP200 clock SCLK, until a 1 is sampled and decoded by the EEPROM as a start bit.
The SCLK signal of the TL16PNP200 connects to the EEPROM clock C. The READ op code (10) is then
sampled on the next two rising edges of SCLK. The TL16PNP200 sources the op code at the falling edges of
SCLK.
C
(SCLK)
S
(SCS)
D/Q
(SIO)
td1
td2
tw(SCLKH)
tw(SCLKL)
Start
Op Code Input = 1
tpd1
Op Code Input = 0
Start
Op Code Input
NOTE A: The corresponding TL16PNP200 terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together with a 2-kΩ resistor.
Figure 9. READ Op Code Transfer
READ address and data transfer (see Figure 10)
After receiving the READ op code, the EEPROM samples the READ address on the next eight rising edges of
SCLK. The device sources the address at the falling edge of SCLK. The EEPROM then sends out a dummy
bit 0 on the D/Q line, which is followed by the 16-bit data word with the MSB first. Output data changes are
triggered by the rising edges of SCLK. The data is also read by the TL16PNP200 on the rising edges of SCLK.
C
(SCLK)
S
(SCS)
D/Q
(SIO)
td2
tpd1
tpd2
tpd3
td3
Address Input
Data Output
NOTE A: The corresponding TL16PNP200 terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together with a 2-kΩ resistor.
Figure 10. READ Address and Data Transfer
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