TL16PNP200 Datasheet, PDF (11/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
system timing requirements and switching characteristics over recommended ranges of supply
voltage and operating free-air temperature
PARAMETER
ALT SYMBOL
FIGURE
TEST
CONDITIONS
MIN MAX UNIT
tw1
Pulse duration, write strobe (IOW)
tWR
6
2
clock
periods
tw2
Pulse duration, read strobe (IOR)
tRD
5
3
clock
periods
tw3
Pulse duration, reset
tRST
tsu1
Setup time, data (D7-D0) valid before IOW↑
tDS
tsu2
Setup time, address (A23-A0) valid before IOW↑
tAS
tsu3
Setup time, address (A23-A0) valid before BALE↓
tBALE
th1
Hold time, data (D7-D0) valid after IOW↑
tDH
th2
Hold time, address (A15-A0) valid after IOW↑
tAH
td4
Delay time, address (A15-A0) valid to IOCSn↓
tIOCSf
td5
Delay time, address (A15-A0) invalid to IOCSn↑
tIOCSr
td6
Delay time, address (A23-A0) valid to MCSn↓
tMCSf
td7
Delay time, address (A23-A0) invalid to MCSn↑
tMCSr
td8
Delay time, IOR↓ to OENn↓
tOENf
td9
Delay time, IOR↑ to OENn↑
tOENr
td10
Delay time, IOR↓ to data (D7-D0) valid
tVD
1
µs
6
10
ns
6
10
ns
6
10
ns
6
5
ns
6
5
ns
5
18 ns
5
14 ns
6
18 ns
6
14 ns
5
15 ns
5
10 ns
After 2-1/2
5
clock
periods
25 ns
td11
Delay time, IOR↑ to data (D7-D0) floating
td12
Delay time, INTRn↑ to IRQm↑
td13
Delay time, INTRn↓ to IRQm↓
td14
Delay time, DMA_RQn↑ to CDRQm↑
td15
Delay time, DMA_RQn↓ to CDRQm↓
td16
Delay time, CDACKm↓ to DMA_ACKn↓
td17
Delay time, CDACKm↑ to DMA_ACKn↑
tHZD
5
tIRQr
7
tIRQf
7
tDRQr
8
tDRQf
8
tDACKf
8
tDACKr
8
20 ns
12 ns
14 ns
9 ns
10 ns
16 ns
12 ns
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
11