TL16PNP200 Datasheet, PDF (19/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
PRINCIPLES OF OPERATION
PnP logical device control registers
The registers in Table 7 are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus.
Table 7. PnP Logical Device Control Registers
ADDRESS PORT
0×30
0×31
REGISTER NAME
ACCESSIBILITY
ACTIVE
Read/write
This register controls whether the logical device is active on the bus.
Bit [7-1] These bits are reserved and must be set to 0.
Bit [0]
If set, this bit activates the logical device.
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, I/O range check
must be disabled.
I/O RANGE CHECK
Read/write
This register is used to perform a conflict check on the I/O port range programmed for use by the logical device.
Bit [7-2] This bit is reserved and must be set to 0.
Bit [1]
If bit is set, the I/O range check is enabled. I/O range check is only valid when the logical device is
inactive.
Bit [0]
If bit 0 is set, the logical device responds to I/O and reads to its assigned I/O range with a 0×55.
If bit 0 is clear, the logical device responds with a 0×AA.
PnP logical device configuration registers
The registers in Table 8 program the device ISA bus resource use and are repeated for each logical device.
Registers in the ISA PnP specification that are not implemented in the TL16PNP200 are reset to 0 when read,
except for the unimplemented DMA channel select descriptor 1 (0x75) which returns a 4 when read.
Table 8. PnP Logical Device Configuration Registers
ADDRESS PORT
REGISTER NAME
0×40
MEMORY BASE ADDRESS [23-16]
ACCESSIBILITY
Read/write
0×41
This register indicates the selected memory base address of bits 23-16.
MEMORY BASE ADDRESS [15-8]
Read/write
This register indicates the selected memory base address of bits 15-8.
0×42
MEMORY CONTROL
Read/write
Bit 1 specifies 8 by 16-bit control. When set bit 1 indicates 16-bit memory, and cleared to indicate 8-bit memory.
Bit 0 is read-only. It is internally set to 1 indicating that the next field is the upper limit for the address. TL16PNP200 supports
memory upper limit, not range length.
0×43
MEMORY UPPER LIMIT ADDRESS [23−16]
Read/write
This register indicates the selected memory upper limit address of bits 23-16.
0×44
MEMORY UPPER LIMIT ADDRESS [15-8]
This register indicates the selected memory upper limit address of bits 15-8.
Read/write
0×60
I/O PORT BASE ADDRESS [15-8]
Read/write
This register indicates bits 15-8 of the base address that are to be used for the selected I/O address range.
0×61
I/O PORT BASE ADDRESS [7-0]
Read/write
This register indicates bits 7-0 of the base address that are to be used for the selected I/O address range.
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