TL16PNP200 Datasheet, PDF (4/23 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200
STANDALONE PLUGĆANDĆPLAY (PnP) CONTROLLER
SLLS229A − NOVEMBER 1995 − REVISED APRIL 1996
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
A15-A0
A16 (INTR2),†
A17 (INTR3),†
A18 (INTR4)†
A19 (CDACK3),†
A20 (CDACK4)†
A21 (CDRQ3),†
A22 (CDRQ4)†
A23 (IOCS4)†
11-26
9-7
6, 5
4, 3
2
I Address. A15-A0 connects to ISA address bits SA15-SA0.
I Address (Interrupt). In Mode 0, A16−A18 should be connected to ISA address bits SA16, LA17, and LA18
respectively. In Mode 1, INTR2−INTR4 are interrupt requests from logical devices 2, 3, and 4 respectively.
I Address (DMA acknowledge). In Mode 0, A19−A20 should be connected to ISA address bits LA19 and
LA20. In Mode 1, CDACK3 and CDACK4 are configurable data acknowledge signals and should be
connected to the ISA DACK signals of the selected DMA channels as specified by DMA mapping in the
power-up defaults.
I/O Address (DMA request). In Mode 0, A21 and A22 are inputs that should be connected to ISA address bits
LA21 and LA22. In Mode 1, CDRQ3 and CDRQ4 are configurable data request outputs and should be
connected to the ISA DRQ signals of the selected DMA channels as specified by DMA mapping in the
power-up defaults.
I/O Address (I/O chip select). In Mode 0, A23 is an input that should be connected to ISA address bit LA23.
In Mode 1, IOCS4 is a I/O chip select output for logical device 4.
AEN
BALE (OEN1)†
40
I ISA address enable. During DMA operation, AEN is an active signal that prevents the controller from
generating an I/O chip select.
80 I/O ISA bus address latch enable (output enable). In Mode 0, BALE is an ISA input which is used to latch the
upper address. In Mode 1, OEN1 is an output enable and can be configured to respond to I/O read
operations to any logical device, which can use it to enable its transceivers.
CDACK0,
CDACK1,
CDACK2
45-43
I Configurable ISA DMA acknowledge. CDACK0 − CDACK2 should be connected to the ISA DACK signals
of the selected DMA channels as specified by DMA mapping in the power-up defaults.
CDRQ0, CDRQ1, 49-47 O Configurable ISA DMA data request. CDRQ0−CDRQ2 should be connected to the ISA DRQ signals of the
CDRQ2
selected DMA channels as specified by DMA mapping in the power-up defaults.
CLK
42
I 10-22 MHz clock. CLK is an input from the OSC signal on the ISA bus.
D0-D7
31-28, I/O 8-bit ISA data
36-33
DMA_ACK0,
DMA_ACK1
67, 66 O DMA acknowledge. DMA_ACK0 and DMA_ACK1 are used for DMA acknowledge to logical devices 0 and
1.
DMA_RQ0,
DMA_RQ1
71, 70 I DMA requests. DMA_RQ0 and DMA_RQ1 are used for DMA requests from logical devices 0 and 1.
GND
1, 27,
37, 61,
74
Ground (0 V). All terminals must be tied to GND for proper operation.
INTR0, INTR1
73, 72 I Interrupt requests. INTR0 and INTR1 generate interrupt requests from logical devices 0 and 1.
IOCS0, IOCS1
75, 76 O I/O chip select outputs to logical devices 0 and 1. The address decoder decodes the full 16-bit I/O address
and generates the I/O chip select signals based on the selected I/O block size.
IOR
38
I ISA I/O read.
IOW
39
I ISA I/O write.
IRQ3−IRQ7,
IRQ9−IRQ12,
IRQ14, IRQ15
MCS0(IOCS3),†
MCS1(IOCS2)†
50-60
78, 77
O ISA Interrupt request. These signals should be connected to the corresponding ISA IRQ signals.
O Memory chip select (I/O chip select). In Mode 0, MCS0 and MCS1 are the memory chip select outputs for
logical devices 0 and 1. A 24-bit memory address is decoded to generate the memory chip select signals
based on the selected memory block size. In Mode 1, IOCS3 and IOCS2 are the I/O chip select outputs
for logical devices 3 and 2.
OEN0
79
O Output enable. OEN0 can be configured to respond to I/O read operations to any logical device, which can
use it to enable its transceivers.
† _{Terminal names in parenthesis indicate when the device is in mode 1 operation.}
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