THS6184_16 Datasheet, PDF (7/39 Pages) Texas Instruments – DUAL-PORT, LOW-POWER DIFFERENTIAL xDSL LINE DRIVER AMPLIFIERS

THS6184
www.ti.com ................................................................................................................................................. SLLS635D – AUGUST 2005 – REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
At V_S = ±5 V: R_F = 3 kΩ, R_L = 50 Ω, G = 5, R_adj = 0, full bias (unless otherwise noted). Each amplifier independently tested
PARAMETER
CONDITIONS
TYP
25°C
25°C
OVER TEMPERATURE
0°C to –40°C
70°C to 85°C
UNITS
MIN/
MAX
Crosstalk
f = 1 MHz,
D1 to D2, D3 to D4
–35
V_O = 2 V_PP
D1 to D3, D2 to D4
–70
dB
Typ
dB
Typ
POWER SUPPLY
Maximum operating voltage
±16
±16
±16
V
Max
Minimum operating voltage
±4
±4
±4
V
Min
Per amplifier, Full (Bias-1 = 0, Bias-2 = 0)
3.9
4.4
4.5
4.6
mA
Max
Per amplifier, Mid (Bias-1 = 1, Bias-2 = 0)
2.9
Maximum Is+ quiescent current
Per amplifier, Low (Bias-1 = 0, Bias-2 = 1)
2
mA
Typ
Per amplifier, Off (Bias-1 = 1, Bias-2 = 1)
0.2
Minimum Is+ quiescent current
Per amplifier, Full (Bias-1 = 0, Bias-2 = 0)
3.9
3.2
3
3
mA
Min
Per amplifier, Full (Bias-1 = 0, Bias-2 = 0)
3.7
4.2
4.3
4.4
mA
Max
Maximum ls– quiescent current
Per amplifier, Mid (Bias-1 = 1, Bias-2 = 0)
2.7
Per amplifier, Low (Bias-1 = 0, Bias-2 = 1)
1.8
mA
Typ
Per amplifier, Off (Bias-1 = 1, Bias-2 = 1)
0.01
Minimum Is- quiescent current
Per amplifier, Full Bias
3.7
3.1
2.9
2.9
mA
Min
Current through GND pin
Per amplifier, Full (Bias-1 = 0, Bias-2 = 0)
0.2
mA
Typ
Power supply rejection (+PSRR)
Power supply rejection (–PSRR)
LOGIC CHARACTERISTICS
Bias control pin logic threshold
V_S+ = 6 V to 4 V, V_S– = –5 V
V_S+ = 5 V, V_S– = –6 V to –4 V
Logic 1, with respect to GND pin⁽¹⁾
Logic 0, with respect to GND pin⁽¹⁾
76
70
68
67
dB
Min
70
64
62
61
dB
Min
≥2.6
V
Typ
≤0.8
V
Typ
Bias pin quiescent current
Bias-X = 0.5 V (Logic 0)
Bias-X = 3.3 V (Logic 1)
1
10
15
15
µA
Max
10
20
30
30
Turn on time delay(t_(ON))
Turn off time delay (t_(Off))
Bias pin input impedance
1
Time for I_S to reach 50% of final value
1
50
µs
Typ
kΩ
Typ
Amplifier output impedance
Off (Bias-1 = 1, bias-2 = 1)
10||5
kΩ||pF
Typ
(1) GND pin useable range is from V_S– to (V_S+ – 2.5 V).
Table 2. LOGIC TABLE⁽¹⁾
BIAS-1
0
1
0
1
BIAS-2
0
0
1
1
FUNCTION
Full Bias Mode
Mid Bias Mode
Low Bias Mode
Shutdown Mode
DESCRIPTION
Amplifiers ON with lowest distortion possible (default state)
Amplifiers ON with power savings with a reduction in distortion performance
Amplifiers ON with enhanced power savings and a reduction of performance
Amplifiers OFF and output has high impedance
(1) Logic pins should not be left floating and should be held by external circuitry to a logic-1 or a logic-0.
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