LMH6517 Datasheet, PDF (7/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

LMH6517
www.ti.com
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
Pin Number
Pin Name
Description
Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0)
2
CLK
Serial Clock
1
SDI
Serial Data In (SPI Compatible) See Application Information for more details.
32
CS
Serial Chip Select (SPI compatible)
31
SDO
Serial Data Out (SPI compatible)
3, 4, 6 — 10, 16, 20, GND
21, 25
Pins unused in Serial Mode, connect to DC ground.
Digital Inputs Pulse Mode (MOD1 = 0 , MOD0 = 1)
2, 7
UPA, UPB
Up pulse pin. A logic 0 pulse will increase gain one step.
1, 8
DNA, DNB
Down pulse pin. A logic 0 pulse will decrease gain one step.
1 & 2 or 7 & 8
Pulsing both pins together will reset the gain to maximum gain.
31, 32
S0A, S1A
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB
10, 9
S0B, S1B
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB
3, 5, 6, 16, 25
GND
Pins unused in Pulse Mode, connect to DC ground.
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