LMH6517 Datasheet, PDF (21/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

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LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
SDI
1
CLK
2
GND
3
GND
4
+3.3/NC
5
GND
6
GND
7
GND
8
LMH6517
GND
24
OPA+
23
OPA-
22
ENA
21
GND
20
GND
19
ENB
18
OPB-
17
OPB+
Figure 50. Pin Functions for Serial Mode
The LMH6517 has a serial interface that allows access to the control registers. The serial interface is a generic
4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers
and DSP controllers.
The serial mode is active when the two mode pins are set as follows: MOD1=1, MOD0=0). In this configuration
the pins function as shown in the pin description table. The SPI interface uses the following signals: clock input
(CLK), serial data in (SDI), serial data out, and serial chip select (CS)
ENA and ENB pins are active in the serial mode. For fast disable capability these pins can be used and the serial
register will hold the last active gain state. These pins will float high and can be left disconnected for serial mode.
The serial control bus can also disable the DVGA channels, but at a much slower speed. The serial enable
function is an AND function. For a channel to be active both the Enable pin and the serial control register must
be in the enabled state. To disable a channel either method will suffice. See Typical Performance Characteristics
for disable and enable timing information.
LATA and LATB pins are not active during serial mode.
CLK: This pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the
rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it
in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled
or disabled.
CS: This pin is the chip select pin. Each assertion starts a new register access - i.e., the SDATA field protocol is
required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the
16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the
case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the
deasserted pulse - which is specified in Electrical Characteristics.
SDI: This pin is an input for the serial data. It must observe setup/hold requirements with respect to the SCLK.
Each cycle is 16-bits long
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