LMH6517 Datasheet, PDF (18/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
www.ti.com
200:
+
LMH6517
-
10 ^0.01P
f = 140 MHz
4.7p ^{220n 12p}
10
.
12p
+IN
100 _{VRM ADC16DV160}
100
-IN
0.01P
Figure 45. Output Configuration
DIGITAL CONTROL
The LMH6517 will support three modes of control, parallel mode, serial mode (SPI compatible) and pulse mode.
Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with
existing SPI compatible systems. The pulse mode is both fast and compact, but must step through intermediate
gain steps when making large gain changes.
The LMH6517 has gain settings covering a range of 31.5 dB. To avoid undesirable signal transients the
LMH6517 should not be powered on with large inputs signals present. Careful planning of system power on
sequencing is especially important to avoid damage to ADC inputs.
The LMH6517 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a
simple voltage divider at each logic pin will allow for this. To properly terminate 100Ω transmission lines a divider
with a 66.5Ω resistor to ground and a 33.2Ω series resistor will properly terminate the line as well as give the
3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic
pins.
Some pins on the LMH6517 have different functions depending on the digital control mode. These functions will
be described in the sections to follow.
Parallel
Serial
Pulse
Reserved
Control Mode
MOD1 Pin Value
1
1
0
0
MOD0 Pin Value
1
0
1
0
PARALLEL MODE (MOD1= 1, MOD0 = 1)
Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space
dedicated to control lines. When designing a system that requires very fast gain changes parallel mode is the
best selection.
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