LMH6517 Datasheet, PDF (23/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

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R/Wb
Reserved
ADDR:
DATA
SCLK
t_CSH
1^st clock
t_CSS
8^th clock
LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
Read / Write bit. A value of 1 indicates a read operation, while a
value of 0 indicates a write operation.
Not used. Must be set to 0.
Address of register to be read or written.
In a write operation the value of this field will be written to the
addressed register when the chip select pin is deasserted. In a read
operation this field is ignored.
16^th clock
t_CSH
t_CSS
CSb
SDO
t_OZD
t_OD
D7 D1
t_ODZ
D0
Figure 53. Read Timing
Table 1. Read Timing
Data Output on SDO Pin
t_CSH
t_CSS
t_OZD
t_ODZ
t_OD
Parameter
Chip select hold time
Chip select setup time
Initial output data delay
High impedance delay
Output data delay
Description
SCLK
t_PL
t_PH
16^th clock
t_SU
t_H
SDI
Valid Data
Valid Data
Figure 54. Write Timing
Data Written to SDI Pin
Table 2. Write Timing
Data Input on SDI Pin
Parameter
t_PL
t_PH
t_SU
t_H
Description
Minimum clock low time (clock duty dycle)
Minimum clock high time (clock duty cycle)
Input data setup time
Input data hold time
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