LMH6517 Datasheet, PDF (4/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
www.ti.com
5V Electrical Characteristics ⁽¹⁾ (continued)
The following specifications apply for single supply with V+ = 5V, Maximum Gain , R_L = 100Ω, V_OUT = 2 V_PP, fin = 150 MHz.
Boldface limits apply at temperature extremes.
Parameter
Test Conditions
Min ⁽²⁾ Typ ⁽³⁾ Max ⁽²⁾
Units
Gain Step Phase Shift
between any two steps
0.5
°
Gain Step Switching Time
15
ns
Power Requirements
ICC
Supply Current
Each channel (two channels per package)
80
91
mA
P
Power
Each Channel
400
mW
ICC
Disabled Supply Current
Each Channel
7.5
mA
All Digital Inputs
Logic Compatibility
TTL, 2.5V CMOS, 3.3V CMOS
VIL
Logic Input Low Voltage
0
0.4
V
VIH
Logic Input High Voltage
2.0
3.6
V
IIH
Logic Input High Input Current
Digital Input Voltage = 3.3V
−110
110
μA
IIL
Logic Input Low Input Current
Digital Input Voltage = 0V
−110
110
μA
Parallel and Pulse Mode Timing
t_GS
Setup Time
t_GH
Hold Time
t_LP
Latch Low Pulse Width
t_PG
Pulse Gap between Pulses
t_PW
Minimum Latch Pulse Width
t_RW
Reset Width
Serial Mode Timing and AC Characteristics
3
ns
3
ns
7
ns
20
ns
20
ns
10
ns
SPI Compatible
f_SCLK
t_PH
t_PL
t_SU
t_H
t_ODZ
Serial Clock Frequency
SCLK High State Duty Cycle
SCLK Low State Duty cycle
Serial Data In Setup Time
Serial Data In Hold Time
Serial Data Out Driven-to- Tri-State
Time
% of SCLK Period
% of SCLK Period
Referenced to Positive edge of CS
10.5
MHz
40
60
%
40
60
%
0.5
ns
5
ns
40
50
ns
t_OZD
Serial Data Out Tri-State-to-Driven Referenced to Negative edge of SCLK
Time
15
20
ns
t_OD
Serial Data Out Output Delay TIme Referenced to Negative edge of SCLK
15
20
ns
t_CSS
Serial Chip Select Setup TIme
Referenced to Positive edge of SCLK
10
5
t_CSH
Serial Chip Select Hold TIme
Referenced to Positive edge of SCLK
10
5
t_IAG
Inter-Access Gap
Minimum time Serial Chip Select pin must
be asserted between accesses.
3
Cycles of
SCLK
4
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