LMH6517 Datasheet, PDF (22/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
www.ti.com
SDO: This is the data output pin. Ths SDO pin is an open drain output and requires an external bias resistor.
See Figure 51 for resistor sizing guidance. This output is normally at TRI-STATE and is driven only when SCSb
is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the
second 8 SCLK falling edges. Upon power-up, the default register address is 00h.
Each serial interface access cycle is exactly 16 bits long as shown in Figure 52. Each signal's function is
described below. the read timing is shown in Figure 53, while the write timing is shown in figure Figure 54.
SCLK
FPGA/DSP/uC/ASIC
Clock out
Chip Select out
Data Out
Data In
LMH6517
CLK
CS
SDI (MOSI)
SDO (MISO)
R
V+ (Logic High)
For SDO (MISO) pin only:
V_OH = V+,
V_OL = (V+) - (R/(R+25)) * V+
SDO
25:
Recommended:
R = 300 Ohms to 2000 Ohms
V+ (Logic) = 2.5V to 3.3V
Figure 51. SDO Pin External Bias Resistor Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCSb
COMMAND FIELD
DATA FIELD
C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
SDI
R/Wb 0 0 0 A3 A2 A1 A0
Write DATA
Reserved (3-bits)
Address (4-bits)
SDO
D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Hi-Z
Read DATA
Single Access Cycle
Data (8-bits)
Figure 52. Serial Interface Protocol (SPI compatible)
22
Submit Documentation Feedback
Product Folder Links: LMH6517
Copyright © 2008–2013, Texas Instruments Incorporated