LMH6517 Datasheet, PDF (5/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

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LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
CONNECTION DIAGRAM
Top View
A3/SDI/DNA 1
A4/CLK/UPA 2
A5 3
MOD0 4
MOD1 5
B5 6
B4/UPB 7
B3/DNB 8
LMH6517
GND
24 OPA+
23 OPA-
22 ENA
21 LATA
20 LATB
19 ENB
18 OPB-
17 OPB+
Figure 1. 32-Pin WQFN Package
See Package Number RTV0032A
PIN DESCRIPTIONS
Pin Number
Pin Name
Description
Analog I/O
30, 11
IPA+, IPB+
Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed
V+ or go below GND by more than 0.5V.
29, 12
IPA−, IPB−
Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or
go below GND by more than 0.5V.
24, 17
OPA+, OPB+
Amplifier non—inverting output. Internally biased to mid supply.
23, 18
OPA−, OPB−
Amplifier inverting output. Internally biased to mid supply.
Power
13, 15, 26, 28,
center pad
GND
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is internally bonded to the
ground pins.
14, 27
+5V
Power supply pins. Valid power supply range is 4.5V to 5.25V.
Common Control Pins
4, 5
MOD0, MOD1
Digital Mode control pins. These pins float to the logic hi state if left unconnected. See below
for Mode settings.
22, 19
ENA, ENB
Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)
25, 16
A0, B0
Gain bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum Gain)
31, 10
A1, B1
Gain bit one = 1dB step
32, 9
A2, B2
Gain bit two = 2dB step
1, 8
A3, B3
Gain bit three = 4dB step
2, 7
A4, B4
Gain bit four = 8dB step
3, 6
A5, B5
Gain bit five = 16dB step
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