LMH6517 Datasheet, PDF (19/34 Pages) National Semiconductor (TI) – Multi Standard, IF and Baseband, Dual, DVGA

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LMH6517
SNOSB19K – NOVEMBER 2008 – REVISED MARCH 2013
A3
1
A4
2
A5
3
+3.3/NC
4
+3.3/NC
5
B5
6
B4
7
B3
8
LMH6517
GND
24
OPA+
23
OPA-
22
ENA
21
LATA
20
LATB
19
ENB
18
OPB-
17
OPB+
Figure 46. Pin Functions for Parallel Mode
The LMH6517 has a 6-bit gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain
control pins is immediately sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin
transitions high the current gain state is held and subsequent changes to the gain set pins are ignored. To
minimize gain change glitches multiple gain control pins should not change while the latch pin is low. In order to
achieve the very fast gain step switching time of 5 ns the internal gain change circuit is very fast. Gain glitches
could result from timing skew between the gain set bits. This is especially the case when a small gain change
requires a change in state of three or more gain control pins. If continuous gain control is desired the Latch pin
can be tied to ground. This state is called transparent mode and the gain pins are always active. In this state the
timing of the gain pin logic transitions should be planned carefully to avoid undesirable transients
ENA and ENB pins are provided to reduce power consumption by disabling the highest power portions of the
LMH6517. The gain register will preserve the last active gain setting during the disabled state. These pins will
float high and can be left disconnected if they won't be used. If the pins are left disconnected a 0.01uF capacitor
to ground will help prevent external noise from coupling into these pins. See Typical Performance Characteristics
for disable and enable timing information.
FPGA/DSP/PC/ASIC
DVGA
latcha
ga[5:0]
gb[5:0]
latchb
pd
latcha
cmode
V_SS
6
ga[5:0]
6
gb[5:0]
latchb
pd
Pins: 15
MSPS: 125
Low Skew
Figure 47. Parallel Mode Connection for Fastest Response
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