DS90CR216A Datasheet, PDF (7/34 Pages) Texas Instruments – 3.3-V Rising Edge Data Strobe LVDS Receiver

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DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016
6.6 Switching Characteristics: Receiver
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
PARAMETER
CLHT LVCMOS Low-to-High Transition Time (Figure 2)
CHLT LVCMOS High-to-Low Transition Time (Figure 2)
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10)
RSPos1 Receiver Input Strobe Position for Bit 1
RSPos2 Receiver Input Strobe Position for Bit 2
RSPos3 Receiver Input Strobe Position for Bit 3
f = 40 MHz
RSPos4 Receiver Input Strobe Position for Bit 4
RSPos5 Receiver Input Strobe Position for Bit 5
RSPos6 Receiver Input Strobe Position for Bit 6
RSPos0
Receiver Input Strobe Position for Bit 0
(Figure 9, Figure 10)
RSPos1 Receiver Input Strobe Position for Bit 1
RSPos2 Receiver Input Strobe Position for Bit 2
RSPos3 Receiver Input Strobe Position for Bit 3
f = 66 MHz
RSPos4 Receiver Input Strobe Position for Bit 4
RSPos5 Receiver Input Strobe Position for Bit 5
RSPos6 Receiver Input Strobe Position for Bit 6
RSKM RxIN Skew Margin⁽²⁾ (Figure 11)
f = 40 MHz
f = 66 MHz
RCOP RxCLK OUT Period (Figure 3)
RCOH RxCLK OUT High Time (Figure 3)
RCOL
RSRC
RxCLK OUT Low Time (Figure 3)
RxOUT Setup to RxCLK OUT (Figure 3)
f = 40 MHz
RHRC RxOUT Hold to RxCLK OUT (Figure 3)
RCOH RxCLK OUT High Time (Figure 3)
RCOL
RSRC
RxCLK OUT Low Time (Figure 3)
RxOUT Setup to RxCLK OUT (Figure 3)
f = 66 MHz
RHRC
RCCD
RPLLS
RxOUT Hold to RxCLK OUT (Figure 3)
RxCLK IN to RxCLK OUT Delay at 25°C, V_CC = 3.3 V⁽³⁾ (Figure 4)
Receiver Phase Lock Loop Set (Figure 5)
RPDD Receiver Power Down Delay (Figure 8)
MIN
TYP
MAX UNIT
2
5 ns
1.8
5 ns
1
1.4
2.15 ns
4.5
5
5.8 ns
8.1
8.5
9.15 ns
11.6
11.9
12.6 ns
15.1
15.6
16.3 ns
18.8
19.2
19.9 ns
22.5
22.9
23.6 ns
0.7
1.1
1.4 ns
2.9
3.3
3.6 ns
5.1
5.5
5.8 ns
7.3
7.7
8 ns
9.5
9.9
10.2 ns
11.7
12.1
12.4 ns
13.9
14.3
14.6 ns
490
ps
400
ps
15
T
50 ns
10
12.2
ns
10
11
ns
6.5
11.6
ns
6
11.6
ns
5
7.6
ns
5
6.3
ns
4.5
7.3
ns
4
6.3
ns
3.5
5
7.5 ns
10 ms
1 μs
(1) Typical Values are given for V_CC = 3.3 V and T_A = 25ºC
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the DS90CR215/DS90CR285 transmitter and DS90CR216A/DS90CR286A receiver is: (T + TCCD) + (2*T
+ RCCD), where T = Clock period.
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