DS90CR216A Datasheet, PDF (4/34 Pages) Texas Instruments – 3.3-V Rising Edge Data Strobe LVDS Receiver

DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016
www.ti.com
DS90CR286A Pin Functions — DGG0056A Package — 28-Bit Channel Link Receiver
PIN
NAME
NO.
I/O , TYPE
PIN DESCRIPTION
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-
10, 9,
12, 11,
16, 15,
20, 19
I, LVDS
Positive and negative LVDS differential data inputs. 100-Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
RxCLKIN+,
18,
RxCLKIN-
17
I, LVDS
Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
RxOUT[27:0]
7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27
O, LVCMOS LVCMOS level data outputs.
RxCLK OUT
26
O, LVCMOS LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN
25
I, LVCMOS LVCMOS level input. When asserted low, the receiver outputs are low.
V_CC
GND
56, 48, 40, 31
52, 44, 36,
28, 4
Power
Power
Power supply pins for LVCMOS outputs.
Ground pins for LVCMOS outputs.
PLL V_CC
PLL GND
23
24, 22
Power
Power
Power supply for PLL.
Ground pin for PLL.
LVDS V_CC
LVDS GND
13
21, 14, 8
Power
Power
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CR216A Pin Functions — DGG0048A Package — 21-Bit Channel Link Receiver
PIN
NAME
NO.
I/O , TYPE
PIN DESCRIPTION
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-
9, 8,
11, 10,
15, 14
I, LVDS
Positive and negative LVDS differential data inputs. 100-Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
RxCLKIN+,
17,
RxCLKIN-
16
I, LVDS
Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
RxOUT[20:0]
5, 4, 2, 1, 47,
46, 45, 43, 41,
40, 39, 37, 35,
34, 33, 31, 30,
29, 27, 26, 24
O, LVCMOS LVCMOS level data outputs.
RxCLK OUT
23
O, LVCMOS LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN
22
I, LVCMOS LVCMOS level input. When asserted low, the receiver outputs are low.
V_CC
GND
48, 42, 36, 28
44, 38, 32,
25, 3
Power
Power
Power supply pins for LVCMOS outputs.
Ground pins for LVCMOS outputs.
PLL V_CC
PLL GND
20
21, 19
Power
Power
Power supply for PLL.
Ground pin for PLL.
LVDS V_CC
LVDS GND
12
18, 13, 7
Power
Power
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
4
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