DS90CR216A Datasheet, PDF (15/34 Pages) Texas Instruments – 3.3-V Rising Edge Data Strobe LVDS Receiver

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DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016
7.3 Feature Description
The DS90CR286A and DS90CR216A consist of several key blocks:
• LVDS Receivers
• Phase Locked Loop (PLL)
• Serial LVDS-to-Parallel LVCMOS Converter
• LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CR286A and four differential LVDS inputs to the
DS90CR216A. Four of the LVDS inputs contain serialized data originating from a 28-bit source transmitter. For
the DS90CR216A, three of the LVDS inputs contain serialized data originating from a 21-bit source transmitter.
The remaining LVDS input contains the LVDS clock associated with the data pairs.
7.3.1.1 LVDS Input Termination
The DS90CR286A and DS90CR216A require a single 100-Ω terminating resistor across the true and
complement lines on each differential pair of the receiver input. To prevent reflections due to stubs, this resistor
should be placed as close to the device input pins as possible. Figure 18 shows an example.
Figure 18. LVDS Serialized Link Termination
7.3.2 Phase Locked Loop (PLL)
The Channel Link I devices use an internal PLL to recover the clock transmitted across the LVDS interface. The
recovered clock is then used as a reference to determine the sampling position of the seven serial bits received
per clock cycle. The width of each bit in the serialized LVDS data stream is one-seventh the clock period.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another) and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Individual bypassing of
each V_CC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock to
improve the overall jitter budget.
7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
After the PLL locks to the incoming LVDS clock, the receiver deserializes each LVDS differential data pair into
seven parallel LVCMOS data outputs per clock cycle. For the DS90CR286A, the LVDS data inputs map to
LVCMOS outputs according to Figure 6. For the DS90CR216A, the LVDS data inputs map to LVCMOS outputs
according to Figure 7.
7.3.4 LVCMOS Drivers
The LVCMOS outputs from the DS90CR286A and DS90CR216A are the deserialized parallel single-ended data
from the serialized LVDS differential data pairs. Each LVCMOS output is clocked by the PLL and strobes on the
RxCLKOUT rising edge. All unused DS90CR286A and DS90CR216A RxOUT outputs can be left floating.
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Product Folder Links: DS90CR216A DS90CR286A DS90CR286A-Q1