DS90CR216A Datasheet, PDF (14/34 Pages) Texas Instruments – 3.3-V Rising Edge Data Strobe LVDS Receiver

DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016
7 Detailed Description
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7.1 Overview
The DS90CR286A and DS90CR286A-Q1 are receivers that convert four LVDS (Low Voltage Differential
Signaling) data streams into parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC, VSYNC, DE,
and CNTL). The DS90CR216A is a receiver that converts three LVDS data streams back into parallel 21 bits of
LVCMOS data (18 bits of RGB and 3 bits of HSYNC, VSYNC, and DE). An internal PLL locks to the incoming
LVDS clock ranging from 20 to 66 MHz. The locked PLL ensures a stable clock to sample the output LVCMOS
data on the Receiver Clock Out rising edge. These devices feature a PWR DWN pin to put the device into low
power mode when there is no active input data.
7.2 Functional Block Diagrams
4 x LVDS Data
(140 to 462 Mbps on
Each LVDS Channel)
28 x LVCMOS
Outputs
LVDS Clock
(20 to 66 MHz)
PLL
Receiver Clock Out
PWR DWN
Figure 16. DS90CR286A Block Diagram
3 x LVDS Data
(140 to 462 Mbps on
Each LVDS Channel)
21 x LVCMOS
Outputs
LVDS Clock
(20 to 66 MHz)
PLL
Receiver Clock Out
PWR DWN
Figure 17. DS90CR216A Block Diagram
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