DS90CR216A Datasheet, PDF (12/34 Pages) Texas Instruments – 3.3-V Rising Edge Data Strobe LVDS Receiver

DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)⁽¹⁾ + ISI (Inter-symbol interference)⁽²⁾
(1) Cycle-to-cycle jitter depends on the Tx source. if a Channel Link I Source Transmitter is used, clock jitter is
maintained to less than 250 ps at 66 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 11. Receiver LVDS Input Skew Margin
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