BQ500101 Datasheet, PDF (7/20 Pages) Texas Instruments – NexFET Power Stage

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bq500101
SLPS585 – MARCH 2016
7.3 Feature Description
7.3.1 Powering bq500101 And Gate Drivers
An external V_DD voltage is required to supply the integrated gate driver device and provide the necessary gate
drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass V_DD pin
to P_GND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap
supply to drive the Control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor C_BOOT
between BOOT and BOOT_R pins. An optional R_BOOT resistor in series with C_BOOT can be used to slow down the
turn on speed of the Control FET and reduce voltage spikes on the V_SW node. A typical 1 Ω to 4.7 Ω value is a
compromise between switching loss and V_SW spike amplitude.
7.3.2 Undervoltage Lockout Protection (UVLO)
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V_VDD rises, both the Control
FET and Sync FET gates hold actively low at all times until V_VDD reaches the higher UVLO threshold (V_{UVLO_H}).,
Then the driver becomes operational and responds to PWM command. If VDD falls below the lower UVLO
threshold (V_{UVLO_L} = V_{UVLO_H} – Hysteresis), the device disables the driver and drives the outputs of the Control
FET and Sync FET gates actively low. Figure 1 shows this function.
VUVLO_H
VUVLO_L
VVDD
Driver On
UDG-12218
Figure 1. UVLO Operation
7.3.3 Integrated Boost-Switch
To maintain a BOOT-V_SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BOOT pin is replaced by a FET which is gated by the DRVL
signal.
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