BQ500101 Datasheet, PDF (13/20 Pages) Texas Instruments – NexFET Power Stage

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9 Layout
bq500101
SLPS585 – MARCH 2016
9.1 Layout Guidelines
9.1.1 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
9.1.2 Electrical Performance
The bq500101 has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then taken
with the PCB layout design and placement of the input capacitors, inductor and switch capacitors (SW
capacitors).
• The placement of the input capacitors relative to V_IN and P_GND pins of bq500101 device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
the ceramic input capacitor C1 needs to be placed as close as possible to the V_IN and P_GND pins (see
Figure 12). Notice if there are input capacitors on both sides of the board, an appropriate amount of V_IN and
GND vias need to be added to interconnect both layers..
• The bootstrap cap C_BOOT 0.1-µF 0603 16-V ceramic capacitor C4 in Figure 12 should be closely connected
between BOOT and BOOT_R pins.
• The switching node of the inductor should be placed relatively close to the Power Stage bq500101 V_SW pins.
Minimizing the V_SW node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. ⁽¹⁾
9.2 Layout Example
L1
GND
GND
C3
VSW
VDD 1
VDD 2
GND 3
4
VSW
8
PWM
7 BOOT
6
9
C4
BOOT_R
5
bq500101
VIN
GND
GND
C1
Figure 12. Recommended PCB Layout (Top Down View)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Copyright © 2016, Texas Instruments Incorporated
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