AM1808_11 Datasheet, PDF (7/265 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
www.ti.com
SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011
Revision History (continued)
See
Section 5.9
EDMA
Section 5.22
External Memory Interface A
(EMIFA)
Section 5.11
DDR2/mDDR Controller
ADDITIONS/MODIFICATIONS/DELETIONS
Section 5.9.1, EDMA Synchronization Events:
• Updated Table 5-12.
Section 5.10.5, EMIFA Electrical Data/Timing:
• Corrected 1.3V, 1.2V MIN value in Table 5-21.
• Updated EMA_A[12:0] to EMA_A[22:0] in Figure 5-12 through Figure 5-15.
• Removed unused parameters 29 and 30 from Figure 5-12.
• Removed unused parameters 31 and 32 from Figure 5-13.
Section 5.11.1, DDR2/mDDR Memory Controller Electrical Data/Timing
• Corrected 1.3V and 1.2 V MAX values in Table 5-23.
Section 5.11.3.8, Net Classes:
• Corrected Table 5-32 column heading.
Section 5.11.3.11, DDR2/mDDR CK and ADDR_CTRL Routing:
• Updated Table 5-35.
• Added last four bullets to list of what SATA Controller supports.
Section 5.14
Serial ATA Controller (SATA)
Section 5.14.2, SATA Interface:
• Updated values in Figure 5-28.
• Updated SATA AC coupling capacitor value unit in Table 5-46.
Section 5.17.2
SPI Electrical Data/Timing
Section 5.17.2.1, Serial Peripheral Interface (SPI) Timing:
• Added t_{ih(SPC_SOMI)M} to Table 5-68.
• Corrected MAX values and updated table note in Table 5-69.
• Updated table note in Table 5-76
• Corrected MAX values and changed table note in Table 5-77.
Section 5.20
Universal Serial Bus OTG
Controller (USB0) [USB2.0
OTG]
• Added Important Notice.
Section 5.20.2, USB0 [USB2.0] Electrical Data/Timing:
• Added first paragraph.
Section 5.22
Ethernet Media Access
Controller (EMAC)
Section 5.22.2, EMAC Electrical Data/Timing
• Added table note to Table 5-102.
Section 5.23
Section 5.23.2, Management Data Input/Output (MDIO) Electrical Data/Timing:
Management Data Input/Output
(MDIO)
• Updated MDIO parameters 4 and 5 in Table 5-105.
Section 5.24
LCD Controller (LCDC)
Section 5.29
Enhanced High-Resolution
Pulse-Width Modulator
(eHRPWM)
Section 5.30.1
Timer Electrical Data/Timing
Section 5.31.1
Clock Source
• Added 2nd paragraph.
Section 5.24.1, LCD Interface Display Driver (LIDD Mode):
• Removed table note for Table 5-108.
• Updated description for parameters 12 and 13 in Table 5-109.
Section 5.24.2, LCD Raster Mode:
• Updated Figure 5-61.
• Extended time line in Figure 5-62.
Table 5-125, eHRPWM Module Control and Status Registers Grouped by Submodule:
• Updated offset addresses for HRCNFG.
Table 5-131, Timing Requirements for Timer Input:
• Updated table note.
Figure 5-83, Clock Source
• Replaced Real Time Clock with RTC Power Source.
Section 5.34
Emulation Logic
Section 6.1
Device Support
• Added Section 5.34.4, IEEE 1149.1 JTAG.
• Added Section 5.34.5, JTAG 1149.1 Boundary Scan Considerations.
Section 6.1.2, Device Nomenclature:
• Updated Figure 6-1.
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