AM1808_11 Datasheet, PDF (110/265 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011
DDR2/mDDR Memory Controller
DDR_D[0]
DDR_D[7]
DDR_DQM[0]
DDR_DQS[0]
DDR_D[8]
DDR_D[15]
DDR_DQM[1]
DDR_DQS[1]
DDR_BA[0]
DDR_BA[2]
DDR_A[0]
DDR_A[13]
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CLKP
DDR_CLKN
DDR_ZP
DDR_DQGATE0
DDR_DQGATE1
T
T
T
T
T
T
T
T
T
T
T
T ⁽¹⁾
T
DDR_VREF
0.1 μF⁽²⁾
T
T
T
T
NC
T
T
T
T
NC
0.1 μF⁽²⁾
0.1 μF⁽²⁾
DDR2/mDDR
ODT
DQ0
DQ7
LDM
LDQS
LDQS
DQ8
DQ15
UDM
UDQS
UDQS
BA0
BA2
A0
A13
CS
CAS
RAS
WE
CKE
CK
CK
VREF⁽³⁾
www.ti.com
DDR_DVDD18
0.1 μF
0.1 μF
1 K Ω 1%
VREF
1 K Ω 1%
T Terminator, if desired. See terminator comments.
(1) See Figure 5-23 for DQGATE routing specifications.
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,
these capacitors can be eliminated completely.
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 5-16. DDR2/mDDR Single-Memory High Level Schematic
110 Peripheral Information and Electrical Specifications
Copyright © 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): AM1808