AM1808_11 Datasheet, PDF (159/265 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011
Table 5-75. Additional SPI0 Slave Timings, 5-Pin Option ^(1)(2)(3) (continued)
NO.
PARAMETER
30 t_{dis(SPC_ENA)S}
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA. ⁽⁴⁾
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
1.3V, 1.2V
MIN
MAX
2.5P+17.5
2.5P+17.5
2.5P+17.5
2.5P+17.5
1.1V
MIN
MAX
2.5P+20
2.5P+20
2.5P+20
2.5P+20
1.0V
MIN
MAX
2.5P+27
2.5P+27
2.5P+27
2.5P+27
UNIT
ns
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
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Peripheral Information and Electrical Specifications 159