AM1808_11 Datasheet, PDF (6/265 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS653A device-specific data
manual to make it an SPRS653B revision. This device is now in the production data (PD) stage of
development.
See
Global
Section 2.5
Pin Assignments
Section 2
Device Overview
Section 2.7
Terminal Functions
Section 2.8
Unused Pin Configurations
Section 4
Device Operating Condtions
Section 5.3
Power Supplies
Section 5.5
Crystal Oscillator or External
Clock Input
Section 5.6
Clock PLLs
Section 5.7
Interrupts
Revision History
ADDITIONS/MODIFICATIONS/DELETIONS
• Replaced CLKIN with OSCIN.
• Removed EMA_A25.
Section 2.5.1, Pin Map (Bottom View):
• Updated pin names in Figure 2-1, Pin Map (Quad A), through Figure 2-4, Pin Map (Quad D).
Table 2-1, Characteristics of the Device:
• Corrected DDR2 max to 156 MHz and mDDR max to 150 MHz.
Table 2-7, External Memory Interface A (EMIFA) Terminal Functions:
• Corrected description for signal A18.
Table 2-9, Serial Peripheral Interface (SPI) Terminal Functions:
• Changed signal type to I/O for signal C16, C18, G17, and H17.
Table 2-12, Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions:
• Changed signal type to Input for signal A4, C16, and D2.
Table 2-14, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:
• Updated signal name for signal F4.
Table 2-20, Ethernet Media Access Controller (EMAC) Terminal Functions:
• Changed signal type to I/O for signal W18.
Table 2-24, Universal Host-Port Interface (UHPI) Terminal Functions:
• Changed signal type to Output for signal R16.
• Added new section.
Section 4.1, Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless
Otherwise Noted):
• Updated ESD Stress Voltage MAX values.
Section 4.2, Recommended Operating Conditions:
• Added DVDD18 under Supply Voltage.
Section 4.3, Notes on Recommended Power-On Hours (POH), added.
Section 4.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted):
• Updated parameters for V_OH and V_OL.
• Updated table notes 1 and 3.
Section 5.3.1, Power-On Sequence:
• Changed VDDA_12_PLL0 to PLL0_VDDA, and VDDA_12_PLL1 to PLL1_VDDA in step 2b.
• Changed last sentence, first paragraph in description.
• Table 5-3, OSCIN Timing Requirements for an Externally Driven Clock, added table note.
Section 5.6.1, PLL Device-Specific Information:
• Updated PLLn to PLL0 or PLL1, as appropriate in Figure 5-8, PLL External Filtering
Components.
• Added paragraph below figure.
• Updated OSCIN area to include DEEPSLEEP Enable in Figure 5-9, PLL Topology.
• Changed PLLREF MAX value in Table 5-4.
Section 5.6.3, Dynamic Voltage and Frequency Scaling (DVFS):
• Updated Maximum internal clock frequency specifications in Table 5-5.
Section 5.7.1.4, AINTC System Interrupt Assignments:
• Updated Interrupt Name and Source columns in Table 5-6.
6
Contents
Submit Documentation Feedback
Product Folder Link(s): AM1808
Copyright © 2010–2011, Texas Instruments Incorporated