AM1808_11 Datasheet, PDF (119/265 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011
Figure 5-22 shows the topology and routing for the DQS and D net class; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
A1
Figure 5-22. DQS and D Routing and Topology
Table 5-35. DQS and D Routing Specification
NO. PARAMETER
1 Center to center DQS to other DDR2/mDDR trace spacing⁽¹⁾
2 DQS/D nominal trace length⁽³⁾⁽⁴⁾
3 D to DQS Skew Length Mismatch⁽⁴⁾
4 D to D Skew Length Mismatch⁽⁴⁾
5 Center to center D to other DDR2/mDDR trace spacing⁽¹⁾⁽⁵⁾
6 Center to Center D to other D trace spacing⁽¹⁾⁽⁶⁾
MIN
4w ⁽²⁾
DQLM-50
4w ⁽²⁾
3w ⁽²⁾
TYP
DQLM
MAX
UNIT
DQLM+50
Mils
100
Mils
100
Mils
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) w = PCB trace width as defined in Table 5-27.
(3) Series terminator, if used, should be located closest to DDR.
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) D's from other DQS domains are considered other DDR2/mDDR trace.
(6) DQLM is the longest Manhattan distance of each of the DQS and D net class.
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Peripheral Information and Electrical Specifications 119
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