MSP430F533_15 Datasheet, PDF (69/112 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
Table 6-24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
System control
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
REGISTER
SYSCTL
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
OFFSET
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Table 6-25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
00h
OFFSET
Table 6-26. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
Port mapping password
Port mapping control
Port P2.0 mapping
Port P2.1 mapping
Port P2.2 mapping
Port P2.3 mapping
Port P2.4 mapping
Port P2.5 mapping
Port P2.6 mapping
Port P2.7 mapping
REGISTER DESCRIPTION
REGISTER
PMAPPWD
00h
PMAPCTL
02h
P2MAP0
00h
P2MAP1
01h
P2MAP2
02h
P2MAP3
03h
P2MAP4
04h
P2MAP5
05h
P2MAP6
06h
P2MAP7
07h
OFFSET
Table 6-27. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
Port P1 input
Port P1 output
Port P1 direction
Port P1 pullup/pulldown enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
Port P2 direction
Port P2 pullup/pulldown enable
REGISTER
P1IN
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
P1IES
P1IE
P1IFG
P2IN
P2OUT
P2DIR
P2REN
OFFSET
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
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Detailed Description
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