MSP430F533_15 Datasheet, PDF (15/112 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at V_CC to V_SS
Voltage applied to any pin (excluding VCORE, VBUS, V18)⁽²⁾
Diode current at any device pin
–0.3
4.1
V
–0.3
V_CC + 0.3
V
±2
mA
Maximum junction temperature, T_J
Storage temperature, T_stg(3)
95
°C
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
V_CC
V_SS
V_BAT,RTC
V_BAT,MEM
T_A
T_J
C_BAK
C_VCORE
C_DVCC/
C_VCORE
Supply voltage during program execution and flash
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =
DV_CC = V_CC) ^{(1) (2)}
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
DVSS2 = DVSS3 = V_SS)
Backup-supply voltage with RTC operational
Backup-supply voltage with backup memory retained
Operating free-air temperature
Operating junction temperature
Capacitance at pin VBAK
Capacitor at VCORE⁽³⁾
Capacitor ratio of DVCC to VCORE
PMMCOREVx = 0
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
T_A = 0°C to 85°C
T_A = –40°C to +85°C
T_A = –40°C to +85°C
I version
I version
MIN NOM MAX UNIT
1.8
3.6
2.0
3.6
V
2.2
3.6
2.4
3.6
0
V
1.55
1.70
1.20
–40
–40
1 4.7
470
3.6
V
3.6
3.6 V
85 °C
85 °C
10 nF
nF
10
(1) TI recommends powering AV_CC and DV_CC from the same source. A maximum difference of 0.3 V between AV_CC and DV_CC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22
for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
Copyright © 2010–2015, Texas Instruments Incorporated
Specifications
15
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