MSP430F533_15 Datasheet, PDF (18/112 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
www.ti.com
Low-Power Mode Supply Currents (Into V_CC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾
PARAMETER
–40°C
25°C
60°C
85°C
V_CC
PMMCOREVx
TYP
MAX
TYP
MAX
TYP
MAX
TYP
UNIT
MAX
0
0.9
I_LPM3,
Low-power mode 3,
VLO mode, Watchdog
3V
1
0.9
VLO,WDT
enabled ^{(7) (4)}
2
1.0
3
1.0
1.2 1.9 4.0
1.2
4.1
1.3
4.2
1.3 2.2 4.3
5.9 10.3
6.0
µA
6.1
6.3 11.3
0
0.9
1.1 1.8 3.9
5.8
10
I_LPM4
Low-power mode 4⁽⁸⁾⁽⁴⁾ 3 V
1
2
0.9
1.0
1.1
1.2
4.0
4.1
5.9
µA
6.1
3
1.0
1.2 2.1 4.2
6.2
11
Low-power mode 3.5
I_LPM3.5,
RTC,VCC
(LPM3.5) current with
active RTC into primary
3V
supply pin DV_CC ⁽⁹⁾
Low-power mode 3.5
I_LPM3.5,
RTC,VBAT
(LPM3.5) current with
active RTC into backup
3V
supply pin VBAT⁽¹⁰⁾
0.5
0.8 1.4 µA
0.6
0.8 1.4 µA
I_LPM3.5,
Total low-power mode
3.5 (LPM3.5) current
3V
RTC,TOT
with active RTC⁽¹¹⁾
1.0
1.1
1.3
1.6 2.8 µA
I_LPM4.5
Low-power mode 4.5
(LPM4.5) ⁽¹²⁾
3V
0.2
0.3 0.6 0.7
0.9 1.4 µA
(7) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK = f_MCLK = f_SMCLK = f_DCO = 0 MHz
LDO disabled (LDOEN = 0).
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO = f_ACLK = f_MCLK = f_SMCLK = 0 MHz
LDO disabled (LDOEN = 0).
(9) V_VBAT = V_CC - 0.2 V, f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(10) V_VBAT = V_CC - 0.2 V, f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(11) f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
(12) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO = f_ACLK = f_MCLK = f_SMCLK = 0 MHz
5.6 Thermal Resistance Characteristics
θ_JA
θ_JC(TOP)
θ_JB
PARAMETER
Junction-to-ambient thermal resistance, still air⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
QFP (PZ)
BGA (ZQW)
QFP (PZ)
BGA (ZQW)
QFP (PZ)
BGA (ZQW)
VALUE
122
108
83
72
98
76
UNIT
°C/W
°C/W
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
18
Specifications
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