G2R-14-12VDC Datasheet, PDF (69/73 Pages) Texas Instruments – Ultralow Power NTSC/PAL/SECAM Video Decoder With RObust Sync Detector

4 Example Register Settings
The following example register settings are provided only as a reference. These settings, given the assumed input
connector, video format, and output format, set up the TVP5150A decoder and provide video output. Example register
settings for other features and the VBI data processor are not provided here.
4.1 Example 1
4.1.1 Assumptions
Input connector:
Composite (AIP1A)
Video format:
NTSC-M or PAL (B, G, H, I)
NOTE: NTSC-443, PAL-N, PAL-M, and SECAM are masked from the autoswitch process by
default. See the autoswitch mask register at address 04h.
Output format:
8-bit ITU-R BT.656 with embedded syncs
4.1.2 Recommended Settings
Recommended I²C writes: For this setup, only one write is required. All other registers are set up by default.
I²C register address 03h = Miscellaneous controls register address
I²C data 09h = Enables YCbCr output and the clock output
NOTE: HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the
miscellaneous control register at address 03h.
4.2 Example 2
4.2.1 Assumptions
Input connector:
Video format:
Output format:
S-video (AIP1A (luma), AIP1B (chroma))
NTSC-M, 443, PAL (B, G, H, I, M, N) and SECAM (B, D,G, K, KI, L)
8-bit 4:2:2 YCbCr with discrete sync outputs
4.2.2 Recommended Settings
Recommended I²C writes: This setup requires additional writes to output the discrete sync 4:2:2 data outputs, the
HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above.
I²C register address 00h = Video input source selection #1 register
I²C data 01h = Selects the S-Video input, AIP1A (luma), and AIP1B (chroma)
I²C register address 03h = Miscellaneous controls register address
I²C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO
I²C register address 04h = Autoswitch mask register
I²C data C0h = Unmask NTSC-443, PAL-N, PAL-M, and SECAM from the autoswitch process
I²C register address 0Dh = Outputs and data rates select register
I²C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output
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